Low power operation of Very-Large-Scale Integration (VLSI) circuits is becoming essential for saving power in current and future processors. Furthermore, power efficiency has become one of the primary competitive metrics for System-On-Chip (SOC) designs in computer, processor, cell-phone, tablet, micro-server and net-book markets. However, it is becoming increasingly challenging to lower the dynamic power consumption for nano-scale process technology based processors (e.g., sub 22-nm) due to higher intrinsic device variations (e.g., variations in effective channel length Le and threshold voltage Vt of a transistor) and sensitivity to defects that cause failures at low voltages.
SOC designs are also becoming increasingly desirable and competitive in the cell phone, tablet, micro-server and net-book market spaces. However, due to the complexity of various functional units on SOC designs, and challenging tradeoff of power versus performance, global power supply (Vcc) SOC rail voltage can vary vastly from SOC design to design. This variation in Vcc poses several challenges for circuits e.g., Static Random Access Memory (SRAM) and other memory designs.